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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Device Pin-to-Pin Output Parameter Guidelines
Table 41: Clock-Capable Clock Input to Output Delay Without MMCM/PLL (Near Clock Region)
Speed Grade
Symbol
Description
Device
-3
-2/-2L
1.0V
-1
-1M
0.9V
-2L
Units
SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, without MMCM/PLL.
T ICKOF
Clock-capable clock input and OUTFF
without MMCM/PLL (near clock region)
XC7K70T
XC7K160T
XC7K325T
XC7K355T
XC7K410T
XC7K420T
XC7K480T
XQ7K325T
XQ7K410T
4.98
5.23
5.72
5.34
5.84
5.50
5.50
N/A
N/A
5.49
5.77
6.31
5.87
6.44
6.04
6.04
6.31
6.44
6.17
6.48
7.09
6.57
7.22
6.77
6.77
7.09
7.22
N/A
N/A
N/A
N/A
N/A
N/A
N/A
7.09
7.22
7.04
7.38
8.07
7.51
8.21
7.73
7.73
8.07
8.21
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1.
Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
Table 42: Clock-Capable Clock Input to Output Delay Without MMCM/PLL (Far Clock Region)
Speed Grade
Symbol
Description
Device
-3
-2/-2L
1.0V
-1
-1M
0.9V
-2L
Units
SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, without MMCM/PLL.
T ICKOFFAR
Clock-capable clock input and OUTFF
without MMCM/PLL (far clock region)
XC7K70T
XC7K160T
XC7K325T
XC7K355T
XC7K410T
XC7K420T
XC7K480T
XQ7K325T
XQ7K410T
5.29
5.84
6.33
5.95
6.45
6.41
6.41
N/A
N/A
5.83
6.45
6.99
6.55
7.12
7.06
7.06
6.99
7.12
6.55
7.24
7.84
7.32
7.97
7.90
7.90
7.84
7.97
N/A
N/A
N/A
N/A
N/A
N/A
N/A
7.84
7.97
7.47
8.24
8.92
8.36
9.07
9.01
9.01
8.92
9.07
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1.
Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
DS182 (v2.8) March 4, 2014
Product Specification
www.xilinx.com
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